PCM TDM API - Qualcomm Dragonwing Documentation

Header: spf/api/modules/pcm_tdm_api.h

Structures

`param_id_hw_pcm_intf_cfg_t`

Members

uint32_t

}

uint32_t

uint16_t

}

uint16_t

to the driver with other masters.

uint32_t

uint16_t

}

`param_id_tdm_intf_cfg_t`

Members

uint32_t

}

uint32_t

uint16_t

}

uint16_t

to the driver with other masters.

uint32_t

uint16_t

data for synchronization.

uint16_t

}

`param_id_tdm_lane_cfg_t`

Members

uint16_t

1 to ((2^N)-1), where N is the number of physical lanes supported by the hardware interface. Bits 0 to N-1 correspond to lanes 0 to N-1. When a bit is set, the corresponding lane is active. The number of active lanes can be inferred from the number of bits set in the mask.}

uint16_t

}

Type Definitions

`param_id_hw_pcm_intf_cfg_t`

typedef struct param_id_hw_pcm_intf_cfg_t param_id_hw_pcm_intf_cfg_t

`param_id_tdm_intf_cfg_t`

typedef struct param_id_tdm_intf_cfg_t param_id_tdm_intf_cfg_t

`param_id_tdm_lane_cfg_t`

typedef struct param_id_tdm_lane_cfg_t param_id_tdm_lane_cfg_t

Macros

`PORT_ID_HW_PCM_INPUT`

#define PORT_ID_HW_PCM_INPUT 0x2

`PORT_ID_HW_PCM_OUTPUT`

#define PORT_ID_HW_PCM_OUTPUT 0x1

`PCM_TDM_STACK_SIZE`

#define PCM_TDM_STACK_SIZE 2048

`PCM_INTF_TYPE_PRIMARY`

#define PCM_INTF_TYPE_PRIMARY 0

`PCM_INTF_TYPE_SECONDARY`

#define PCM_INTF_TYPE_SECONDARY 1

`PCM_INTF_TYPE_TERTIARY`

#define PCM_INTF_TYPE_TERTIARY 2

`PCM_INTF_TYPE_QUATERNARY`

#define PCM_INTF_TYPE_QUATERNARY 3

`PCM_INTF_TYPE_QUINARY`

#define PCM_INTF_TYPE_QUINARY 4

`PCM_SYNC_SRC_EXTERNAL`

Enumeration for the auxiliary PCM synchronization signal provided by an external source.

#define PCM_SYNC_SRC_EXTERNAL 0x0

`PCM_SYNC_SRC_INTERNAL`

Enumeration for the auxiliary PCM synchronization signal provided by an internal source.

#define PCM_SYNC_SRC_INTERNAL 0x1

`PCM_CTRL_DATA_OE_DISABLE`

Enumeration for disabling the PCM/TDM configuration ctrl_data_out_enable parameter.

#define PCM_CTRL_DATA_OE_DISABLE 0x0

`PCM_CTRL_DATA_OE_ENABLE`

Enumeration for enabling the PCM/TDM configuration ctrl_data_out_enable parameter.

#define PCM_CTRL_DATA_OE_ENABLE 0x1

`PCM_BITS_PER_FRAME_16`

Enumeration for setting the PCM configuration frame to 16.

#define PCM_BITS_PER_FRAME_16 0x0

`PCM_BITS_PER_FRAME_32`

Enumeration for setting the PCM configuration frame to 32.

#define PCM_BITS_PER_FRAME_32 0x1

`PCM_BITS_PER_FRAME_64`

Enumeration for setting the PCM configuration frame to 64.

#define PCM_BITS_PER_FRAME_64 0x2

`PCM_BITS_PER_FRAME_128`

Enumeration for setting the PCM configuration frame to 128.

#define PCM_BITS_PER_FRAME_128 0x3

`PCM_BITS_PER_FRAME_256`

Enumeration for setting the PCM configuration frame to 256.

#define PCM_BITS_PER_FRAME_256 0x4

`PCM_MODE`

Enumeration for the PCM configuration aux_mode parameter, which configures the auxiliary PCM interface to use short synchronization.

#define PCM_MODE 0x0

`AUX_MODE`

Enumeration for the PCM configuration aux_mode parameter, which configures the auxiliary PCM interface to use long synchronization.

#define AUX_MODE 0x1

`PARAM_ID_HW_PCM_INTF_CFG`

Param ID to configure PCM interface.

#define PARAM_ID_HW_PCM_INTF_CFG 0x0800101A

`MODULE_ID_HW_PCM_SINK`

Module ID for PCM sink module.

#define MODULE_ID_HW_PCM_SINK 0x0700100C

`MODULE_ID_HW_PCM_SOURCE`

End of the Module —>

#define MODULE_ID_HW_PCM_SOURCE 0x0700100D

`PORT_ID_TDM_INPUT`

End of the Module —>

#define PORT_ID_TDM_INPUT 0x2

`PORT_ID_TDM_OUTPUT`

#define PORT_ID_TDM_OUTPUT 0x1

`TDM_INTF_TYPE_PRIMARY`

#define TDM_INTF_TYPE_PRIMARY 0

`TDM_INTF_TYPE_SECONDARY`

#define TDM_INTF_TYPE_SECONDARY 1

`TDM_INTF_TYPE_TERTIARY`

#define TDM_INTF_TYPE_TERTIARY 2

`TDM_INTF_TYPE_QUATERNARY`

#define TDM_INTF_TYPE_QUATERNARY 3

`TDM_INTF_TYPE_QUINARY`

#define TDM_INTF_TYPE_QUINARY 4

`TDM_SYNC_SRC_EXTERNAL`

Enumeration for the auxiliary TDM synchronization signal provided by an external source.

#define TDM_SYNC_SRC_EXTERNAL 0x0

`TDM_SYNC_SRC_INTERNAL`

Enumeration for the auxiliary TDM synchronization signal provided by an internal source.

#define TDM_SYNC_SRC_INTERNAL 0x1

`TDM_CTRL_DATA_OE_DISABLE`

Enumeration for disabling the TDM configuration ctrl_data_out_enable parameter.

#define TDM_CTRL_DATA_OE_DISABLE 0x0

`TDM_CTRL_DATA_OE_ENABLE`

Enumeration for enabling the TDM configuration ctrl_data_out_enable parameter.

#define TDM_CTRL_DATA_OE_ENABLE 0x1

`TDM_SHORT_SYNC_BIT_MODE`

Short (one-bit) Synchronization mode.

#define TDM_SHORT_SYNC_BIT_MODE 0

`TDM_LONG_SYNC_MODE`

Long Synchronization mode.

#define TDM_LONG_SYNC_MODE 1

`TDM_SHORT_SYNC_SLOT_MODE`

Short (one-slot) Synchronization mode.

#define TDM_SHORT_SYNC_SLOT_MODE 2

`TDM_SYNC_NORMAL`

Normal synchronization.

#define TDM_SYNC_NORMAL 0

`TDM_SYNC_INVERT`

Invert the synchronization.

#define TDM_SYNC_INVERT 1

`TDM_DATA_DELAY_0_BCLK_CYCLE`

Zero-bit clock cycle synchronization data delay.

#define TDM_DATA_DELAY_0_BCLK_CYCLE 0

`TDM_DATA_DELAY_1_BCLK_CYCLE`

One-bit clock cycle synchronization data delay.

#define TDM_DATA_DELAY_1_BCLK_CYCLE 1

`TDM_DATA_DELAY_2_BCLK_CYCLE`

Two-bit clock cycle synchronization data delay.

#define TDM_DATA_DELAY_2_BCLK_CYCLE 2

`TDM_MAX_SLOTS_PER_FRAME`

Max number of slots per frame supported by TDM interface.

#define TDM_MAX_SLOTS_PER_FRAME 32

`TDM_MAX_CHANNEL_CNT`

max number of channels for tdm interface

#define TDM_MAX_CHANNEL_CNT 32

`PARAM_ID_TDM_INTF_CFG`

Param ID to configure TDM interface.

#define PARAM_ID_TDM_INTF_CFG 0x0800101B

`PARAM_ID_TDM_LANE_CFG`

Param ID to configure TDM lanes.

#define PARAM_ID_TDM_LANE_CFG 0x0800106A

`MODULE_ID_TDM_SINK`

Module ID for TDM sink module.

#define MODULE_ID_TDM_SINK 0x0700100E

`MODULE_ID_TDM_SOURCE`

End of the Module —>

#define MODULE_ID_TDM_SOURCE 0x0700100F

​Structures

​param_id_hw_pcm_intf_cfg_t

​param_id_tdm_intf_cfg_t

​param_id_tdm_lane_cfg_t

​Type Definitions

​param_id_hw_pcm_intf_cfg_t

​param_id_tdm_intf_cfg_t

​param_id_tdm_lane_cfg_t

​Macros

​PORT_ID_HW_PCM_INPUT

​PORT_ID_HW_PCM_OUTPUT

​PCM_TDM_STACK_SIZE

​PCM_INTF_TYPE_PRIMARY

​PCM_INTF_TYPE_SECONDARY

​PCM_INTF_TYPE_TERTIARY

​PCM_INTF_TYPE_QUATERNARY

​PCM_INTF_TYPE_QUINARY

​PCM_SYNC_SRC_EXTERNAL

​PCM_SYNC_SRC_INTERNAL

​PCM_CTRL_DATA_OE_DISABLE

​PCM_CTRL_DATA_OE_ENABLE

​PCM_BITS_PER_FRAME_16

​PCM_BITS_PER_FRAME_32

​PCM_BITS_PER_FRAME_64

​PCM_BITS_PER_FRAME_128

​PCM_BITS_PER_FRAME_256

​PCM_MODE

​AUX_MODE

​PARAM_ID_HW_PCM_INTF_CFG

​MODULE_ID_HW_PCM_SINK

​MODULE_ID_HW_PCM_SOURCE

​PORT_ID_TDM_INPUT

​PORT_ID_TDM_OUTPUT

​TDM_INTF_TYPE_PRIMARY

​TDM_INTF_TYPE_SECONDARY

​TDM_INTF_TYPE_TERTIARY

​TDM_INTF_TYPE_QUATERNARY

​TDM_INTF_TYPE_QUINARY

​TDM_SYNC_SRC_EXTERNAL

​TDM_SYNC_SRC_INTERNAL

​TDM_CTRL_DATA_OE_DISABLE

​TDM_CTRL_DATA_OE_ENABLE

​TDM_SHORT_SYNC_BIT_MODE

​TDM_LONG_SYNC_MODE

​TDM_SHORT_SYNC_SLOT_MODE

​TDM_SYNC_NORMAL

​TDM_SYNC_INVERT

​TDM_DATA_DELAY_0_BCLK_CYCLE

​TDM_DATA_DELAY_1_BCLK_CYCLE

​TDM_DATA_DELAY_2_BCLK_CYCLE

​TDM_MAX_SLOTS_PER_FRAME

​TDM_MAX_CHANNEL_CNT

​PARAM_ID_TDM_INTF_CFG

​PARAM_ID_TDM_LANE_CFG

​MODULE_ID_TDM_SINK

​MODULE_ID_TDM_SOURCE

Structures

`param_id_hw_pcm_intf_cfg_t`

`param_id_tdm_intf_cfg_t`

`param_id_tdm_lane_cfg_t`

Type Definitions

`param_id_hw_pcm_intf_cfg_t`

`param_id_tdm_intf_cfg_t`

`param_id_tdm_lane_cfg_t`

Macros

`PORT_ID_HW_PCM_INPUT`

`PORT_ID_HW_PCM_OUTPUT`

`PCM_TDM_STACK_SIZE`

`PCM_INTF_TYPE_PRIMARY`

`PCM_INTF_TYPE_SECONDARY`

`PCM_INTF_TYPE_TERTIARY`

`PCM_INTF_TYPE_QUATERNARY`

`PCM_INTF_TYPE_QUINARY`

`PCM_SYNC_SRC_EXTERNAL`

`PCM_SYNC_SRC_INTERNAL`

`PCM_CTRL_DATA_OE_DISABLE`

`PCM_CTRL_DATA_OE_ENABLE`

`PCM_BITS_PER_FRAME_16`

`PCM_BITS_PER_FRAME_32`

`PCM_BITS_PER_FRAME_64`

`PCM_BITS_PER_FRAME_128`

`PCM_BITS_PER_FRAME_256`

`PCM_MODE`

`AUX_MODE`

`PARAM_ID_HW_PCM_INTF_CFG`

`MODULE_ID_HW_PCM_SINK`

`MODULE_ID_HW_PCM_SOURCE`

`PORT_ID_TDM_INPUT`

`PORT_ID_TDM_OUTPUT`

`TDM_INTF_TYPE_PRIMARY`

`TDM_INTF_TYPE_SECONDARY`

`TDM_INTF_TYPE_TERTIARY`

`TDM_INTF_TYPE_QUATERNARY`

`TDM_INTF_TYPE_QUINARY`

`TDM_SYNC_SRC_EXTERNAL`

`TDM_SYNC_SRC_INTERNAL`

`TDM_CTRL_DATA_OE_DISABLE`

`TDM_CTRL_DATA_OE_ENABLE`

`TDM_SHORT_SYNC_BIT_MODE`

`TDM_LONG_SYNC_MODE`

`TDM_SHORT_SYNC_SLOT_MODE`

`TDM_SYNC_NORMAL`

`TDM_SYNC_INVERT`

`TDM_DATA_DELAY_0_BCLK_CYCLE`

`TDM_DATA_DELAY_1_BCLK_CYCLE`

`TDM_DATA_DELAY_2_BCLK_CYCLE`

`TDM_MAX_SLOTS_PER_FRAME`

`TDM_MAX_CHANNEL_CNT`

`PARAM_ID_TDM_INTF_CFG`

`PARAM_ID_TDM_LANE_CFG`

`MODULE_ID_TDM_SINK`

`MODULE_ID_TDM_SOURCE`