I2S API - Qualcomm Dragonwing Documentation

Header: spf/api/modules/i2s_api.h

Structures

`param_id_i2s_intf_cfg_t`

Members

uint32_t

}

uint32_t

}

uint16_t

}

Type Definitions

`param_id_i2s_intf_cfg_t`

typedef struct param_id_i2s_intf_cfg_t param_id_i2s_intf_cfg_t

Macros

`I2S_INTF_TYPE_PRIMARY`

#define I2S_INTF_TYPE_PRIMARY 0

`I2S_INTF_TYPE_SECONDARY`

#define I2S_INTF_TYPE_SECONDARY 1

`I2S_INTF_TYPE_TERTIARY`

#define I2S_INTF_TYPE_TERTIARY 2

`I2S_INTF_TYPE_QUATERNARY`

#define I2S_INTF_TYPE_QUATERNARY 3

`I2S_INTF_TYPE_QUINARY`

#define I2S_INTF_TYPE_QUINARY 4

`I2S_SD0`

Enumeration for setting the I2S configuration sd_line_idx parameter to serial data wire number 0 (SD0).

#define I2S_SD0 0x1

`I2S_SD1`

Enumeration for setting the I2S configuration sd_line_idx parameter to serial data wire number 1 (SD1).

#define I2S_SD1 0x2

`I2S_SD2`

Enumeration for setting the I2S configuration sd_line_idx parameter to serial data wire number 2 (SD2).

#define I2S_SD2 0x3

`I2S_SD3`

Enumeration for setting the I2S configuration sd_line_idx parameter to serial data wire number 3 (SD3).

#define I2S_SD3 0x4

`I2S_QUAD01`

Enumeration for setting the I2S configuration sd_line_idx parameter to SD0 and SD1.

#define I2S_QUAD01 0x5

`I2S_QUAD23`

Enumeration for setting the I2S configuration sd_line_idx parameter to SD2 and SD3.

#define I2S_QUAD23 0x6

`I2S_6CHS`

Enumeration for setting the I2S configuration sd_line_idx parameter to six channels.

#define I2S_6CHS 0x7

`I2S_8CHS`

Enumeration for setting the I2S configuration sd_line_idx parameter to 8 channels.

#define I2S_8CHS 0x8

`CONFIG_I2S_WS_SRC_EXTERNAL`

Enumeration for setting the I2S configuration ws_src parameter to external.

#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0

`CONFIG_I2S_WS_SRC_INTERNAL`

Enumeration for setting the I2S configuration ws_src parameter to internal.

#define CONFIG_I2S_WS_SRC_INTERNAL 0x1

`PORT_ID_I2S_INPUT`

#define PORT_ID_I2S_INPUT 0x2

`PORT_ID_I2S_OUTPUT`

#define PORT_ID_I2S_OUTPUT 0x1

`I2S_STACK_SIZE`

On MDMs, audio runs in root PD.

#define I2S_STACK_SIZE 2048

`PARAM_ID_I2S_INTF_CFG`

Parameter used to configure the I2S interface

#define PARAM_ID_I2S_INTF_CFG 0x08001019

`MODULE_ID_I2S_SINK`

Module ID for I2S sink module.

#define MODULE_ID_I2S_SINK 0x0700100A

`MODULE_ID_I2S_SOURCE`

End of the Module —>

#define MODULE_ID_I2S_SOURCE 0x0700100B

​Structures

​param_id_i2s_intf_cfg_t

​Type Definitions

​param_id_i2s_intf_cfg_t

​Macros

​I2S_INTF_TYPE_PRIMARY

​I2S_INTF_TYPE_SECONDARY

​I2S_INTF_TYPE_TERTIARY

​I2S_INTF_TYPE_QUATERNARY

​I2S_INTF_TYPE_QUINARY

​I2S_SD0

​I2S_SD1

​I2S_SD2

​I2S_SD3

​I2S_QUAD01

​I2S_QUAD23

​I2S_6CHS

​I2S_8CHS

​CONFIG_I2S_WS_SRC_EXTERNAL

​CONFIG_I2S_WS_SRC_INTERNAL

​PORT_ID_I2S_INPUT

​PORT_ID_I2S_OUTPUT

​I2S_STACK_SIZE

​PARAM_ID_I2S_INTF_CFG

​MODULE_ID_I2S_SINK

​MODULE_ID_I2S_SOURCE

Structures

`param_id_i2s_intf_cfg_t`

Type Definitions

`param_id_i2s_intf_cfg_t`

Macros

`I2S_INTF_TYPE_PRIMARY`

`I2S_INTF_TYPE_SECONDARY`

`I2S_INTF_TYPE_TERTIARY`

`I2S_INTF_TYPE_QUATERNARY`

`I2S_INTF_TYPE_QUINARY`

`I2S_SD0`

`I2S_SD1`

`I2S_SD2`

`I2S_SD3`

`I2S_QUAD01`

`I2S_QUAD23`

`I2S_6CHS`

`I2S_8CHS`

`CONFIG_I2S_WS_SRC_EXTERNAL`

`CONFIG_I2S_WS_SRC_INTERNAL`

`PORT_ID_I2S_INPUT`

`PORT_ID_I2S_OUTPUT`

`I2S_STACK_SIZE`

`PARAM_ID_I2S_INTF_CFG`

`MODULE_ID_I2S_SINK`

`MODULE_ID_I2S_SOURCE`