Header: spf/api/modules/audio_hw_clk_api.h
Structures
audio_hw_clk_cfg_req_param_t
Immediately following this structure is a variable length array of audio_hw_clk_cfg_t or clock ID structure.
Members
Number of clock ID’s being configured.
audio_hw_clk_cfg_t
Members
Unique Clock ID of the clock being requested.
Clock frequency in Hz to set.
Divider for two clocks that are coupled, if necessary: divider = A/B, where A is the dividend and B is the divisor.
audio_hw_clk_rel_cfg_t
Members
Unique Clock ID of the clock being released.
audio_hw_clk_rsp_cfg_t
Immediately following this structure is a variable length array of audio_hw_clk_status_cfg_t structure.
Members
Number of failures while requesting for 1 or more clock ID’s.
audio_hw_clk_status_cfg_t
Members
Unique Clock ID of the clock which failed to be requested/released.
Status representing why clock id request/release failed @ Non-Zero - Failure.
Type Definitions
audio_hw_clk_cfg_req_param_t
audio_hw_clk_cfg_t
audio_hw_clk_rel_cfg_t
audio_hw_clk_rsp_cfg_t
audio_hw_clk_status_cfg_t
Macros
PARAM_ID_RSC_AUDIO_HW_CLK
Param ID for audio hardware clocks This ID should only be used under PRM module instance Eg: Bit clocks for audio h/w interface like MI2S, PCM, TDM Mclks for audio codec (internal / external) operation.
CLOCK_ID_MI2S_RANGE_START
Start of the range of MI2S clock IDs.
CLOCK_ID_PRI_MI2S_IBIT
Clock ID of the primary MI2S internal bit clock (IBIT).
CLOCK_ID_PRI_MI2S_EBIT
Clock ID of the primary MI2S external bit clock (EBIT).
CLOCK_ID_SEC_MI2S_IBIT
Clock ID of the secondary MI2S IBIT.
CLOCK_ID_SEC_MI2S_EBIT
Clock ID of the secondary MI2S EBIT.
CLOCK_ID_TER_MI2S_IBIT
Clock ID of the tertiary MI2S IBIT.
CLOCK_ID_TER_MI2S_EBIT
Clock ID of the tertiary MI2S EBIT.
CLOCK_ID_QUAD_MI2S_IBIT
Clock ID of the quaternary MI2S IBIT.
CLOCK_ID_QUAD_MI2S_EBIT
Clock ID of the quaternary MI2S EBIT.
CLOCK_ID_QUI_MI2S_IBIT
Clock ID of the quinary MI2S IBIT.
CLOCK_ID_QUI_MI2S_EBIT
Clock ID of the quinary MI2S EBIT.
CLOCK_ID_QUI_MI2S_OSR
Clock ID of the quinary MI2S OSR.
CLOCK_ID_SEN_MI2S_IBIT
Clock ID of the senary MI2S IBIT.
CLOCK_ID_SEN_MI2S_EBIT
Clock ID of the senary MI2S EBIT.
CLOCK_ID_SEP_MI2S_IBIT
Clock ID of the septenary MI2S IBIT.
CLOCK_ID_SEP_MI2S_EBIT
Clock ID of the sepetnary MI2S EBIT.
CLOCK_ID_HS_I2S_IF0_IBIT
Clock ID of the High speed I2S interface 0 IBIT.
CLOCK_ID_HS_I2S_IF0_EBIT
Clock ID of the high speed I2S interface 0 EBIT.
CLOCK_ID_HS_I2S_IF1_IBIT
Clock ID of the High speed interface 1 IBIT.
CLOCK_ID_HS_I2S_IF1_EBIT
Clock ID of the high speed interface 1 EBIT.
CLOCK_ID_HS_I2S_IF2_IBIT
Clock ID of the High speed interface 2 IBIT.
CLOCK_ID_HS_I2S_IF2_EBIT
Clock ID of the high speed interface 2 EBIT.
CLOCK_ID_HS_I2S_IF3_IBIT
Clock ID of the High speed interface 3 IBIT.
CLOCK_ID_HS_I2S_IF3_EBIT
Clock ID of the high speed interface 3 EBIT.
CLOCK_ID_HS_I2S_IF4_IBIT
Clock ID of the High speed interface 4 IBIT.
CLOCK_ID_HS_I2S_IF4_EBIT
Clock ID of the high speed interface 4 EBIT.
CLOCK_ID_MI2S_RANGE_END
End of the range of MI2S clock IDs.
CLOCK_ID_PCM_RANGE_START
Start of the range of PCM clock IDs.
CLOCK_ID_PRI_PCM_IBIT
Clock ID of the primary PCM IBIT.
CLOCK_ID_PRI_PCM_EBIT
Clock ID of the primary PCM EBIT.
CLOCK_ID_SEC_PCM_IBIT
Clock ID of the secondary PCM IBIT.
CLOCK_ID_SEC_PCM_EBIT
Clock ID of the secondary PCM EBIT.
CLOCK_ID_TER_PCM_IBIT
Clock ID of the tertiary PCM IBIT.
CLOCK_ID_TER_PCM_EBIT
Clock ID of the tertiary PCM EBIT.
CLOCK_ID_QUAD_PCM_IBIT
Clock ID of the quaternary PCM IBIT.
CLOCK_ID_QUAD_PCM_EBIT
Clock ID of the quaternary PCM EBIT.
CLOCK_ID_QUI_PCM_IBIT
Clock ID of the quinary PCM IBIT.
CLOCK_ID_QUI_PCM_EBIT
Clock ID of the quinary PCM EBIT.
CLOCK_ID_QUI_PCM_OSR
Clock ID of the quinary PCM OSR.
CLOCK_ID_SEN_PCM_IBIT
Clock ID of the senary PCM IBIT.
CLOCK_ID_SEN_PCM_EBIT
Clock ID of the senary PCM EBIT.
CLOCK_ID_SEP_PCM_IBIT
Clock ID of the septenary PCM IBIT.
CLOCK_ID_SEP_PCM_EBIT
Clock ID of the septenary PCM EBIT.
CLOCK_ID_HS_PCM_IF0_IBIT
Clock ID of the High speed PCM interface 0 IBIT.
CLOCK_ID_HS_PCM_IF0_EBIT
Clock ID of the high speed PCM interface 0 EBIT.
CLOCK_ID_HS_PCM_IF1_IBIT
Clock ID of the High speed PCM interface 1 IBIT.
CLOCK_ID_HS_PCM_IF1_EBIT
Clock ID of the high speed PCM interface 1 EBIT.
CLOCK_ID_HS_PCM_IF2_IBIT
Clock ID of the High speed PCM interface 2 IBIT.
CLOCK_ID_HS_PCM_IF2_EBIT
Clock ID of the high speed PCM interface 2 EBIT.
CLOCK_ID_HS_PCM_IF3_IBIT
Clock ID of the High speed PCM interface 3 IBIT.
CLOCK_ID_HS_PCM_IF3_EBIT
Clock ID of the high speed PCM interface 3 EBIT.
CLOCK_ID_HS_PCM_IF4_IBIT
Clock ID of the High speed PCM interface 4 IBIT.
CLOCK_ID_HS_PCM_IF4_EBIT
Clock ID of the high speed PCM interface 4 EBIT.
CLOCK_ID_PCM_RANGE_END
End of of the range of PCM clock IDs.
CLOCK_ID_TDM_RANGE_START
Start of the TDM clock ID group.
CLOCK_ID_PRI_TDM_IBIT
Clock ID for the primary TDM IBIT.
CLOCK_ID_PRI_TDM_EBIT
Clock ID for the primary TDM EBIT.
CLOCK_ID_SEC_TDM_IBIT
Clock ID for the secondary TDM IBIT.
CLOCK_ID_SEC_TDM_EBIT
Clock ID for the secondary TDM EBIT.
CLOCK_ID_TER_TDM_IBIT
Clock ID for the tertiary TDM IBIT.
CLOCK_ID_TER_TDM_EBIT
Clock ID for the tertiary TDM EBIT.
CLOCK_ID_QUAD_TDM_IBIT
Clock ID for the quaternary TDM IBIT.
CLOCK_ID_QUAD_TDM_EBIT
Clock ID for the quaternary TDM EBIT.
CLOCK_ID_QUI_TDM_IBIT
Clock ID for the quinary TDM IBIT.
CLOCK_ID_QUI_TDM_EBIT
Clock ID for the quinary TDM EBIT.
CLOCK_ID_QUI_TDM_OSR
Clock ID for the quinary TDM OSR.
CLOCK_ID_SEN_TDM_IBIT
Clock ID for the senary TDM IBIT.
CLOCK_ID_SEN_TDM_EBIT
Clock ID for the senary TDM EBIT.
CLOCK_ID_SEP_TDM_IBIT
Clock ID of the septenary TDM IBIT.
CLOCK_ID_SEP_TDM_EBIT
Clock ID of the septenary TDM EBIT.
CLOCK_ID_HS_TDM_IF0_IBIT
Clock ID of the High speed TDM interface 0 IBIT.
CLOCK_ID_HS_TDM_IF0_EBIT
Clock ID of the high speed TDM interface 0 EBIT.
CLOCK_ID_HS_TDM_IF1_IBIT
Clock ID of the High speed TDM interface 1 IBIT.
CLOCK_ID_HS_TDM_IF1_EBIT
Clock ID of the high speed TDM interface 1 EBIT.
CLOCK_ID_HS_TDM_IF2_IBIT
Clock ID of the High speed TDM interface 2 IBIT.
CLOCK_ID_HS_TDM_IF2_EBIT
Clock ID of the high speed TDM interface 2 EBIT.
CLOCK_ID_HS_TDM_IF3_IBIT
Clock ID of the High speed TDM interface 3 IBIT.
CLOCK_ID_HS_TDM_IF3_EBIT
Clock ID of the high speed TDM interface 3 EBIT.
CLOCK_ID_HS_TDM_IF4_IBIT
Clock ID of the High speed TDM interface 4 IBIT.
CLOCK_ID_HS_TDM_IF4_EBIT
Clock ID of the high speed TDM interface 4 EBIT.
CLOCK_ID_TDM_RANGE_END
End of the TDM clock ID group.
CLOCK_ID_MCLK_RANGE_START
Start of the range of MCLK clock IDs.
CLOCK_ID_MCLK_1
Clock ID for MCLK 1.
CLOCK_ID_MCLK_2
Clock ID for MCLK 2.
CLOCK_ID_MCLK_3
Clock ID for MCLK 3.
CLOCK_ID_MCLK_4
Clock ID for MCLK 4.
CLOCK_ID_MCLK_5
Clock ID for MCLK 5.
CLOCK_ID_WSA_CORE_MCLK
Clock ID for MCLK for WSA core.
CLOCK_ID_WSA_CORE_NPL_MCLK
Clock ID for NPL MCLK for WSA core.
CLOCK_ID_WSA_CORE_2X_MCLK
Clock ID for 2X WSA MCLK (2X MCLK or NPL MCLK, both are same)
CLOCK_ID_VA_CORE_MCLK
Clock ID for MCLK for VA core.
CLOCK_ID_VA_CORE_2X_MCLK
Clock ID for 2X VA MCLK (2X MCLK)
CLOCK_ID_TX_CORE_MCLK
Clock ID for MCLK for TX.
CLOCK_ID_TX_CORE_NPL_MCLK
Clock ID for NPL MCLK for TX.
CLOCK_ID_TX_CORE_2X_MCLK
Clock ID for TX CORE 2X MCLK (2X MCLK or NPL MCLK, both are same)
CLOCK_ID_RX_CORE_MCLK
Clock ID for MCLK for RX.
CLOCK_ID_RX_CORE_NPL_MCLK
Clock ID for NPL MCLK for RX.
CLOCK_ID_RX_CORE_2X_MCLK
Clock ID for RX CORE 2X MCLK (2X MCLK or NPL MCLK, both are same)
CLOCK_ID_WSA2_CORE_MCLK
Clock ID for MCLK for WSA2 core.
CLOCK_ID_WSA2_CORE_2X_MCLK
Clock ID for NPL MCLK for WSA2 core.
CLOCK_ID_RX_CORE_TX_MCLK
Clock ID for RX Core TX MCLK.
CLOCK_ID_RX_CORE_TX_2X_MCLK
Clock ID for RX CORE TX 2X MCLK.
CLOCK_ID_WSA_CORE_TX_MCLK
Clock ID for WSA core TX MCLK.
CLOCK_ID_WSA_CORE_TX_2X_MCLK
Clock ID for WSA core TX 2X MCLK.
CLOCK_ID_WSA2_CORE_TX_MCLK
Clock ID for WSA2 core TX MCLK.
CLOCK_ID_WSA2_CORE_TX_2X_MCLK
Clock ID for WSA2 core TX 2X MCLK.
CLOCK_ID_RX_CORE_MCLK2_2X_MCLK
Clock ID for RX CORE MCLK2 2X MCLK.
CLOCK_ID_MCLK_RANGE_END
End of the range of MCLK clock IDs.
CLOCK_ID_SPDIF_RANGE_START
Start of the range of SPDIF clock IDs.
CLOCK_ID_PRI_SPDIF_OUTPUT_CORE
Clock ID for the primary SPDIF output core.
CLOCK_ID_SEC_SPDIF_OUTPUT_CORE
Clock ID for the secondary SPDIF output core.
Clock ID for the primary SPDIF input core.
Clock ID for the secondary SPDIF input core.
CLOCK_ID_PRI_SPDIF_OUTPUT_NPL
Clock ID for the secondary SPDIF output NPL clk.
CLOCK_ID_SEC_SPDIF_OUTPUT_NPL
Clock ID for the primary SPDIF output NPL clk.
CLOCK_ID_SPDIF_RANGE_END
End of the range of SPDIF clock IDs.
MAX_AUD_HW_CLK_NUM_REQ
Max number of clock ids that can be requested/released at a command.
CLOCK_ATTRIBUTE_INVALID
Clock attribute is invalid (reserved for internal use).
CLOCK_ATTRIBUTE_COUPLE_NO
Clock attribute for no coupled clocks.
CLOCK_ATTRIBUTE_COUPLE_DIVIDEND
Clock attribute for the dividend of the coupled clocks.
CLOCK_ATTRIBUTE_COUPLE_DIVISOR
Clock attribute for the divisor of the coupled clocks.
CLOCK_ATTRIBUTE_INVERT_COUPLE_NO
Clock attribute for the invert-and-no-couple case.
HW_INTF_CLK_ID_DEFAULT
HW_INTF_CLK_FREQ_DEFAULT
HW_INTF_CLK_ATTRI_DEFAULT
CLOCK_ROOT_DEFAULT
Default root clock source.
CLOCK_ROOT_SRC_DEFAULT
Default clock source.
CLOCK_ROOT_SRC_XO
Xo Clock source.
CLOCK_ROOT_SRC_RCO
RCO Clock source.
CLOCK_ROOT_SRC_MAX
maximum clock sources.
