UART

uart7: serial@99c000 {
/* Manufacturer model of serial driver */
compatible = "qcom,geni-uart";
/* SE address and size */
reg = <0 0x0099c000 0 0x4000>;
/*Clocks for SE */
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
clock-names = "se";
/* pinctrl setting */
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
				interconnect-names = "qup-core", "qup-config";
/* To enable QUPV3 serial engine instance for UART protocol, change status to "okay" */
				status = "disabled";
			};
		}

qup_uart7_cts: qup-uart7-cts-state {
				pins = "gpio28";
				function = "qup07";
			};

			qup_uart7_rts: qup-uart7-rts-state {
				pins = "gpio29";
				function = "qup07";
			};

			qup_uart7_tx: qup-uart7-tx-state {
				pins = "gpio30";
				function = "qup07";
			};

			qup_uart7_rx: qup-uart7-rx-state {
				pins = "gpio31";
				function = "qup07";
			};

UART_PROPERTIES devices =
{
   // MAIN_PORT
   0x00994000,    // Serial Engine Base address
   0x009C0000,// qup_common base address
   0x2001c161,  // GPIO TX pin Config
   0x2000c171,  // GPIO RX Pin Config
   0,           // gpio_cts_config
   0,           // gpio_rfr_config
   0,           // clock_id_index
   (void*)0,        // bus_clock_id
   (void*)CLK_QUPV3_WRAP0_S5,     // core_clock_id
   0,          // irq number not used
   0,  //TCSR base
   0,  // TCSR offset
   0   // TCSR value

};

<!--
GPIO configuration calculation

GPIO DIR values
GPIO_INPUT = 0x0
GPIO_OUTPUT = 0x1

GPIO_PULL values
GPIO_NO_PULL = 0, /**< -- Do not specify a pull. */
GPIO_PULL_DOWN = 0x1, /**< -- Pull the GPIO down. */
GPIO_KEEPER_ENABLE = 0x2, /**< -- Keeper Enable. */
GPIO_PULL_UP = 0x3, /**< -- Pull the GPIO up. */

GPIO_DRV_STRENGTH values
GPIO_2P0MA = 0, /**< -- Specify a 2 mA drive. */
GPIO_4P0MA = 0x1, /**< -- Specify a 4 mA drive. */
GPIO_6P0MA = 0x2, /**< -- Specify a 6 mA drive. */
GPIO_8P0MA = 0x3, /**< -- Specify a 8 mA drive. */

GPIO_FUNC_SELECT_Value
GPIO_FS_VAL =0, //Specifies GPIO function

GPIO_FS_VAL =0X1, //Specify NON GPIO function( UART/SPI/I2C)
	
GPIO configuration = (GPIO_NUM & 0xFF) << 0x10 |
(GPIO_FS_VAL & 0xF) << 0xC |
(GPIO_DRV_STRENGTH & 0xF) << 0x8 |
(GPIO_PULL & 0xF) << 0x4 |
(GPIO_DIR & 0xF)

-->
/*
| RESERVED | GPIO NUM | DRIVE | FUNC | PULL | DIR |
-------------------------------------------------------------------------
| 0000 | 0000 | 0001 | 1110 | 0001 | 0001 | 0010 | 0001 |
-------------------------------------------------------------------------
*/

                   offset,        protocol,   mode,  load_fw, dfs_mode
se_cfg se0_cfg = { 0x80000, SE_PROTOCOL_I3C,    GSI,     TRUE, TRUE  };
se_cfg se1_cfg = { 0x84000, SE_PROTOCOL_I2C,    GSI,     TRUE, TRUE  };
se_cfg se2_cfg = { 0x88000, SE_PROTOCOL_I2C,    GSI,     TRUE, TRUE  };
se_cfg se3_cfg = { 0x8C000, SE_PROTOCOL_I2C,    GSI,     FALSE, TRUE  };
se_cfg se4_cfg = { 0x90000, SE_PROTOCOL_SPI,    GSI,     TRUE, TRUE };
se_cfg se5_cfg = { 0x94000, SE_PROTOCOL_UART,   FIFO,    TRUE,FALSE };
se_cfg se6_cfg = { 0x98000, SE_PROTOCOL_UART,   FIFO,    TRUE,FALSE  };

{      .instance_id          =  6 ,         //Instance ID
        .qup              =  QUP_SSC,    //QUP Type
        .se_index         =  5,          //SE ID
        .se_data          =  NULL,       //devcfg_map
        .protocol_io_cfg  =  {
                                TLMM_MAP(TLMM_GPIO_KEEPER ,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER ),              //SLEEP CFG
                                TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_6MA,TLMM_GPIO_KEEPER ),              //SPI CFG
                                TLMM_MAP(TLMM_GPIO_NO_PULL,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL),              //UART CFG
                                TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_NO_PULL),              //I2C CFG
                                TLMM_MAP(TLMM_GPIO_PULL_UP,TLMM_GPIO_2MA,TLMM_GPIO_KEEPER )               //I3C CFG
                             },
        .se_exclusive     =  TRUE,
}

TLMM_MAP (active state pull type, drive strength, sleep state pull type)

--- a/arch/arm64/boot/dts/qcom/<chipset>.dtsi
+++ b/arch/arm64/boot/dts/qcom/<chipset>.dtsi
@@ -70,6 +70,7 @@
 		spi13 = &spi13;
 		spi14 = &spi14;
 		spi15 = &spi15;
+		serial1 = &uart7;
}; 


+
+&uart7 {
+	status = "ok";
+}; 

mount -t debugfs none /sys/kernel/debug
echo -n "file qcom_geni_serial.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file qcom-geni-se.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file serial_core.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file gpi.c +p" > /sys/kernel/debug/dynamic_debug/control