RTSS sleep feature overview

Each core tracks its idle duration using a dedicated idle counter. The counter is incremented on every FreeRTOS tick. When the counter exceeds 30,000 ticks, the core becomes eligible to enter sleep. The sleep eligibility check is performed in the FreeRTOS idle hooks:

• The primary idle hook runs on the idle task of the primary core.
• The passive idle hook runs on secondary cores when no tasks are available for execution.

Both hooks verify whether the idle counter has reached the sleep threshold. If the threshold is reached, control is transferred to the central sleep routine. After wakeup, the idle counter is reset to zero. The system must remain idle for another 30,000 ticks before sleep can be entered again.

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All cores idle requirement

Core 0 doesn’t enter wait for interrupt (WFI) unless all active cores in the system are idle. A global atomic counter tracks the number of cores that are ready for sleep. Before entering WFI, core 0 compares this value against the active core count. If any active core is still processing work, core 0 exits the sleep entry sequence, resets its idle counter, and waits for the next sleep opportunity. The active core count is determined during scheduler initialization based on a GPIO boot configuration pin:

• In lock-step cluster mode, three cores are considered active.
• In normal mode, all four cores are considered active.

This mechanism allows sleep synchronization to adapt automatically to the current hardware configuration.

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Wakeup sequence

Secondary core wakeup Secondary cores (core 1, core 2, and core 3) exit WFI when a peripheral interrupt assigned to the respective core is received. Examples include interrupts from CAN, IPCC, and other peripheral sources. Core 0 wakeup The primary wakeup mechanism for core 0 is an IPCC interrupt. After a secondary core wakes from a hardware interrupt, it invokes IPCC_Trigger to notify core 0 through the IPCC channel. This notification causes core 0 to exit WFI.